1. Field of the Invention
The present invention relates to a reception device.
2. Description of the Background Art
Japanese Patent Application Laid-Open No. 2007-201842 discloses a passive optical network (PON) system including a station-side terminating device (OLT: optical line terminal) and a line terminating device (ONU: optical network unit). In the PON system disclosed in Japanese Patent Application Laid-Open No. 2007-201842, the OLT generates a transmission signal synchronized with a clock signal which has a predetermined frequency and is synchronized with a reference clock signal for synchronization generated by a station-side reference clock source. Accordingly, the ONU reproduces a clock signal from the transmission signal from the OLT, converts a frequency of the clock signal into a predetermined frequency, and generates a reference clock signal for use in Ethernet (registered trademark) equipment.
Japanese Patent Application Laid-Open No. 2011-9984 discloses a gigabit Ethernet-passive optical network (GEPON) system including a station-side device and a terminal-side device. In the GEPON system disclosed in Japanese Patent Application Laid-Open No. 2011-9984, a station-side device uses a device clock generated from a network reference clock as an operation clock, generates transmission data by adding time stamp information to input data, generates correlation information representing a correlation between the network reference clock and the time stamp information, and multiplexes the generated correlation information into downlink data. The terminal-side device reproduces the network reference clock based on the time stamp information and the correlation information included in the transmission data transmitted from the station-side device.
Japanese Patent Application Laid-Open No. 2003-283332 discloses a synchronization circuit including a clock selector, a phase control unit, a phase information storage unit, and a frequency offset control unit. The clock selector outputs a selected clock having a desired phase from a multi-phase clock. The phase control unit outputs a phase control signal based on a comparison result of phases of input data and the selected clock. The phase information storage unit stores phase information from the phase control unit, and controls the clock selector. The frequency offset control unit outputs an offset control signal according to the number of phase control signal outputs, and outputs an offset control signal according to a cumulative number when the cumulative number of the phase control signal exceeds an activation threshold value.
Japanese Patent Application Laid-Open No. 2007-43460 discloses a bit synchronization circuit having an initial phase determination unit. The initial phase determination unit detects a variation point of a reception signal using a multi-phase clock during a preamble reception period of burst data, and outputs initial phase information including a phase number of a clock synchronized with the variation point.
U.S. Pat. No. 7,692,499 discloses a system including a phase-frequency comparator, a storage unit, an adaptive filter, and a digital control oscillator. The phase/frequency comparator detects an error between a reference clock and a feedback clock. The storage unit stores a model which predicts frequency fluctuation of a temperature-compensated crystal oscillator. The adaptive filter includes a loop filter and an algorithm for predicting frequency fluctuation based on a model, and generates a selected output signal based on filter data and prediction data. The digital control oscillator sets a phase of an output clock signal according to an output signal of the adaptive filter. The adaptive filter receives an error signal and outputs filter data in a normal time in which a reference clock is valid, and outputs prediction data in a holdover time in which a reference clock is invalid.
As disclosed in Japanese Patent Application Laid-Open Nos. 2007-201842 and 2011-9984, a reference clock (synchronous clock) can be generated using a clock reproduction unit provided in the ONU.
However, a reception data signal received by the ONU from the OLT is affected by fluctuation within the OLT or noise in a transmission process. In a data reproduction clock signal reproduced based on the reception data signal, frequency fluctuation is large (a cutoff frequency of jitter transfer characteristics from the reception data signal to the clock signal for reproducing data is too high). Therefore, the above-described reproduction clock signal cannot be used as a synchronous clock signal.
In addition, it is also necessary to use a clock signal (transmission clock signal) synchronized with an OLT-side clock signal in generation of a transmission signal to be transmitted to the OLT. The clock signal for reproducing data also cannot be used as a transmission clock signal because frequency fluctuation is too large.
In addition, as in U.S. Pat. No. 7,692,499, technology for supplying a synchronous clock signal for a holdover time based on data stored for a normal time is well known. However, in particular, as in Japanese Patent Application Laid-Open No. 2003-283332, when a clock signal of a desired phase is generated as a synchronous clock signal by performing selection from a multi-phase clock or mixing a multi-phase clock signal, data to be stored is not particularly obvious.